Implantable stimulation devices generate and deliver electrical stimuli to nerves and tissues to treat various biological disorders. Examples include pacemakers to treat cardiac arrhythmia, defibrillators to treat cardiac fibrillation, cochlear stimulators to treat deafness, and various neural stimulators to treat urinary incontinence, sleep apnea, shoulder subluxation, etc. Implantable stimulation devices may be used within various implantable medical device systems. For example, an implantable stimulation device may comprise a Spinal Cord Stimulator (SCS), such as that disclosed in U.S. Pat. No. 6,516,227. However, the present invention may find applicability in any implantable medical device system.
As shown in FIGS. 1A-1C, an SCS system typically includes an Implantable Pulse Generator (IPG) 10, which includes a biocompatible device case 12 formed of titanium for example. The case 12 typically holds the circuitry and battery 14 necessary for the IPG 10 to function, although IPGs can also be powered via external RF energy, without a battery. The IPG 10 is coupled to electrodes 16 via one or more electrode leads (two such leads 18 and 20 are shown) such that the electrodes 16 form an electrode array. The electrodes 16 are carried on a flexible body 24, which also houses the individual signal wires 22 coupled to each electrode. In the illustrated embodiment, there are eight electrodes on lead 18, labeled E1-E8, and eight electrodes on lead 20, labeled E9-E16, although the number of arrays and electrodes is application specific and therefore can vary. The leads 18 and 20 couple to the IPG 10 using lead connectors 26 fixed in a header 28. The IPG 10 has a telemetry coil 32 for communications and charging coil 34 for receiving charging energy from an external charger to charge the IPG's battery 14. (FIG. 1B shows the IPG 10 with the case 12 removed to ease the viewing of the two coils 32 and 34).
As shown in the cross-section of FIG. 1C, the IPG 10 typically includes a printed circuit board (PCB) 30, upon which various electronic components 38 are mounted. The electronic components 38 can include an Application Specific Integrated Circuit (ASIC), such as that disclosed in U.S. Patent Application Publication 2013/0023943. Such an ASIC contains a number of circuit modules that perform various functions of within the IPG including, for example, delivery of stimulation, battery charging functions, and telemetry.
Often, such modules require a regulated, stable, noise-free, and accurate voltage source as a power supply, which can be provided by a regulation system 5 including a linear voltage regulator 50 as illustrated in FIG. 2. Voltage regulator 50 generates a regulated voltage source, Vload, from another power supply, Vin, resident in the IPG 10. For example, Vin can comprise the voltage of the IPG's battery 14. Voltage regulator 50 can be incorporated into the ASIC along with the modules it powers.
The architecture of the conventional linear voltage regulator 50 includes an error amplifier 52, a pass element 54, a reference voltage circuit 56, and a feedback circuit 58. The error amplifier 52 (discussed later in greater detail with respect to FIG. 3) has an inverting input 62 (−), a non-inverting input 60 (+), and an output 64. The non-inverting input 60 (+) is coupled to a reference voltage Vref which is output from the reference voltage circuit 56. The reference voltage circuit 56 may be a band-gap generator, or other suitable voltage reference circuit. The feedback circuit 58, here, is a voltage divider comprising a first feedback resistor R1 and a second feedback resistor R2 connected in series between the output (Vload) of the voltage regulator 50 and ground (GND). The voltage divider output (feedback voltage) 66 serves as the feedback connection to the inverting input 62 of the amplifier 52.
The error amplifier output 64 is coupled to the gate of the pass element 54, realized here using a large PMOS transistor to improve the efficiency of the regulator. The source of the PMOS transistor is connected to Vin and its drain is connected to the feedback circuit 58 and to output Vload of the regulator 50.
The pass element 54 behaves as a variable power switch turning more “on” or “off” depending on the change in the feedback circuit output 66. The error amplifier output 64 controls the voltage drop across the pass element 54 to control the output voltage Vload. For example, as the load current Iload increases, Vload will temporarily decrease which causes the feedback voltage 66 to decrease. The error amplifier 52 tries to force the voltages at its inputs 60 and 62 to be equal and will decrease its output 64 to make the pass element 54 more conductive, which increases Vload to bring it back to its original level. One skilled in the art will recognize therefore that Vload is a function of Vref and the resistances used in the feedback circuit 58.
The regulator's output Vload is coupled to a load 70, which may include a number of circuit modules 72a-c in the IPG 10, such as those mentioned earlier. Different modules 72 may be active and requiring power at a given time, and so Iload will increase or decrease as the different modules 72 are enabled or disabled. Enabling or disabling of the modules 72 is accomplished using a controller 80 (e.g., a microcontroller), which may control other functions in the IPG 10 as well. The controller 80 understands by virtue of its programming which modules 72 are needed at a given time, and so can enable such modules via load enable signals 82. Each module 72a-c receives a unique load enable signal 82a-c. As one skilled understands, enabling a particular module (say 72b via load enable signal 82b) will couple that module to Vload, thus allowing it to be powered and operate as required. Other disabled modules are decoupled from Vload.
To assist with keeping Vload constant when Iload changes, a smoothing capacitor C is coupled to Vload. The size (i.e., width/length) of the pass element 54 and the value of C are generally chosen in accordance with a maximum expected Iload, i.e., when all modules 72a-c are active.
FIG. 3 is a circuit diagram for the error amplifier 52 which employs a conventional a CMOS differential amplifier. The amplifier output 64, as discussed previously, drives the pass element 54 of FIG. 2. The amplifier inputs 60 and 62 are coupled to the gates of input NMOS transistors 86a and 86b forming a differential pair 90. The amplifier 52 has an active load 88, shown here as a current mirror with PMOS load elements 84a and 84b. Error amplifier 52 can be built in different manners, as one skilled in the art understands.
The amplifier 52 also comprises a fixed biasing circuit 92 for providing a fixed bias current Ibias for the amplifier 52. The bias current Ibias provides a constant current sink, which is generated by a current mirror comprised of NMOS load elements 94a and 94b. A reference current, Iref, is provided to the current mirror, and the value of Ibias is scaled from Iref depending on the relative sizes of load elements 94a and 94b; if the transistors 94a and 94b are the same size, Ibias=N*Iref, where N represents a number of transistors 94b wired in parallel.
A minimum Ibias is required to operate the error amplifier 52. However, Ibias is instead typically set to a higher-than-minimum value to handle large swings in Iload. This is because, as the inventors recognize, a high value for Ibias will allow the amplifier 52 to react more quickly to large swings in Iload; in other words, the slew rate of amplifier output 64 increases as Ibias is increased. The inventors recognize the use of high Ibias as unfortunate, as Ibias generally draws current from the IPG's battery 14, which tends to deplete the battery faster, and thus requiring more frequent battery recharging.
FIG. 4 illustrates another problem associated with voltage regulator 50 relating to stability. FIG. 4 shows a Bode plot 95 of the open loop gain characteristics of the regulator 50 for different levels of Iload. Curve 96 shows the open loop gain under a minimum Iload, which occurs when most or all of the modules 72 are deactivated. Curve 97 shows the open loop gain under a maximum Iload, i.e., when most or all of the modules 72 are active. Dominant poles (Po) and secondary poles (Pa) are shown for each of these extreme load conditions. Po is associated with the output of pass element 54, in particular output capacitor C, while Pa is associated with the output resistance and capacitance of the error amplifier 52 including parasitics associated with the pass element 54.
As shown by the arrows in FIG. 4, poles Po and Pa move closer together as Iload increases. This threatens regulator stability, as the regulator may become unstable when more than one pole occurs above the 0 dB threshold. In other words, regulator 50 is susceptible to instability at higher values of Iload.
Prior art techniques to improve stability and slew rate generally involve adding power-hungry circuitry or complex feedback circuits. Therefore, there exists a need for a simple linear voltage regulator that consumes less power without compromising speed of operation or stability.